Zhiru Zhang, Associate Professor in the School of Electrical and Computer Engineering, has been elevated to IEEE Fellow, recognized for contributions to field-programmable gate array high-level synthesis and accelerator design. This is the highest grade of IEEE membership and a milestone career achievement.
“I am truly humbled and honored to be named among a distinguished class of 2023 IEEE Fellows,” Zhang said. “This is a great recognition of the progress we have made towards making high-level synthesis mainstream to enable productive and high-quality accelerator design.
Zhang expressed deep gratitude to his Ph.D. advisor Professor Jason Cong at UCLA for his support and guidance over the years. He added, “I also wanted to share the credit with my former colleagues at AutoESL and Xilinx, my collaborators and co-authors, and all members of my research group at Cornell.”
Zhang’s research focuses on the design and design automation of non-traditional, heterogeneous computer architectures that integrate special-purpose hardware accelerators. These accelerators are crucial to sustaining the performance improvements post Moore’s Law, especially for many emerging application domains such as big data analytics, genomics, and machine learning.
In particular, his work on high-level synthesis (HLS) has made reconfigurable silicon, namely FPGAs, far more accessible by allowing domain experts to build hardware accelerators with software programming languages. His early efforts on C-based HLS systems were successfully commercialized and later acquired by Xilinx (now part of AMD). The resulting HLS tool is now known as Vivado HLS, which has been widely used in industry as well as academia for both research and teaching.
Each year, following a rigorous evaluation procedure, the IEEE Fellow Committee recommends a select group of recipients for elevation to IEEE Fellow, and less than 0.1% of voting members are selected annually for this member grade elevation.