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Zhiru Zhang receives NSF CAREER Award to improve the future of computing
Zhang's work will improve computer performance under tight power and energy efficiency constraints.
ECE’s Zhiru Zhang recently received the prestigious NSF CAREER Award for his proposal, “Synthesizing Highly Efficient Hardware Accelerators for Irregular Programs: A Synergistic Approach”. His work will be an important step towards addressing the severe power and energy constraints that threaten to disrupt the long-standing trend towards ever-increasing computing performance relied upon by virtually all aspects of our lives.
Systems across the computing spectrum are becoming increasingly power-limited. With billions of transistors packed tightly onto a single chip, it is no longer feasible to turn on all the transistors at once due to thermal issues—think how your smartphone gets hot when you have too many applications running. As a result, the portion of the chip we can afford to activate at a given time must run even faster and consume much less energy. For this reason, hardware specialization is gaining attraction in emerging computer architectures, where hardware accelerators customized in certain functionality are extensively used to deliver orders-of-magnitude increase in performance and energy efficiency for important applications.
Zhang envisions that future computers will continue to incorporate a wide range of hardware accelerators for a variety of application domains. He hopes to develop an integrated design automation framework based on high-level languages to allow domain experts to quickly design higher-quality accelerators without going through the laborious, manual, and error-prone hardware design process.
The proposed design automation framework anchors on the fundamental challenges raised by irregular programs, commonplace in emerging application domains such as computer vision, data mining, machine learning, physical simulation, and social network analytics. While gaining prominence, irregular programs are organized around less-regular data structures and are especially difficult to parallelize with conventional architectures.
Zhang proposes a synergistic hardware/software co-design approach to overcome the many challenges raised by irregular program. More specifically, Zhang plans to devise new algorithms and optimization techniques in a novel architectural synthesis engine that generates softly synthesized accelerators capable of carrying out intelligent run-time optimization without incurring significant hardware overhead.
Find the award abstract at http://www.nsf.gov/awardsearch/showAward?AWD_ID=1453378