Suh receives award for paper at VLSI Symposium

Cornell ECE Associate Professor G. Edward Suh and his colleagues recently received a Most Frequently Cited Paper Award (2000-2009) at the 2017 Symposium on VLSI Circuits in Kyoto, Japan. Their paper, “A technique to build a secret key in integrated circuits for identification and authentication applications,” originally presented during the 2004 Symposium on VLSI Circuits, has been most often cited (by 138 papers and by 409 papers on Google Scholar) among all papers that were presented at the Symposia on VLSI Circuits from 2000-2009.

According to the abstract, the paper describes a technique that exploits the statistical delay variations of wires and transistors across integrated circuits to build a secret key unique to each integrated circuit. The paper was authored by Jae W. Lee, Daihyun Lim, Blaise Gassend, G. Edward Suh; Marten van Dijk, and Srinivas Devadas.

An award presentation was held during the 30th Anniversary celebration of Symposia on VLSI Circuits on June 6, 2017 at Rihga Royal Hotel Kyoto, Kyoto, Japan.

Suh is an Associate Professor of Electrical and Computer Engineering at Cornell University and a member of the Computer Systems Laboratory. He received a Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT) with his work on a single-chip secure processor. Following MIT, he spent a year at Verayo Inc., where he led the development of unclonable RFIDs and secure embedded processors. He joined the faculty of the School of Electrical and Computer Engineering at Cornell in 2007.

Suh's research interests include computer systems with particular focus on computer architecture. He is interested in combining architectural techniques with low-level software to enhance various aspects of computing systems such as performance, security and reliability. His recent research efforts focus on building verifiably secure computing systems with an application to secure autonomous driving, and developing architecture frameworks and design methodologies for efficient parallel hardware accelerators.