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The ECE Colloquium is the School's flagship seminar series, featuring general-interest talks from high-profile and engaging speakers drawn from both academia and industry. The talks occur on alternating Mondays during the semester, with refreshments served at 4:15 p.m. and the talks beginning at 4:30 p.m. in 233 Phillips Hall. The current schedule of speakers is as follows...

Parallelism: A serious goal or a silly mantra (...and what else is needed for the Microprocessor of 2024)

Monday, Oct 6, 2014 at 4:30 PM until 6:00 PM [.ics]
PH233

Dr. Yale N. Patt

Area: Computer Architecture

The microprocessor of 2024 will have two things going for it: more than 50 billion transistors on each chip and an opportunity to properly harness the transformation hierarchy.  We hear a lot about the parallelism that one will get from those 50 billion transistors, but very little about what rethinking the transformation hierarchy will enable.  In fact, almost everyone in the computer industry these days seems to be promoting parallelism, whether or not they have any clue whatsoever as to what they are talking about.  Most of the preoccupation is due in large part to the highly visible and well advertised continuing (temporarily) benefits of Moore's Law, manifest by more and more cores on a chip.  More cores = more opportunity for parallelism.  By 2024, we will clearly have more than 1000 cores on a chip -- whether we can effectively utilize them or not does not seem to curb the enthusiasm.  What I would like to do today is examine parallelism, note that it did not start with the multicore chip, observe some of the silliness it has recently generated, identify its fundamental pervasive element, and discuss some of the problems that have surfaced due to its major enabler, Moore's Law.  I would also like to try to show how the transformation hierarchy can turn the bad news of Moore's Law into good news, and play an important role in the microprocessor of 2024.

Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, directing the research of eight PhD students, and consulting in the microprocessor industry.  Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his unconventional approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Jeram Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.  He has received the highest honors in his field for both his reasearch (the 1996 IEEE/ACM Eckert-Mauchly Award) and teaching (the 2000 ACM Karl V. Karlstrom Outstanding Educator Award).  He was the inaugural recipient of the recently established IEEE Computer Society Bob Rau Award in 2011, and was named the 2013 recipient of the IEEE Harry Goode Award.  He is a Fellow of both IEEE and ACM, and a member of the National Academy of Engineering.  More detail can be found on his web page 

www.ece.utexas.edu/~patt.

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