NSF Early Career
ECE’s Zhiru Zhang recently received the prestigious NSF CAREER Award for his proposal, “Synthesizing Highly Efficient Hardware Accelerators for Irregular Programs: A Synergistic Approach”. His work will be an important step towards addressing the severe power and energy constraints that threaten to disrupt the long-standing trend towards ever-increasing computing performance relied upon by virtually all aspects of our lives.
Systems across the computing spectrum are becoming increasingly power-limited. With billions of transistors packed tightly onto a single chip, it is no longer feasible to turn on all the transistors at once due to thermal issues—think how your smartphone gets hot when you have too many applications running. As a result, the portion of the chip we can afford to activate at a given time must run even faster and consume much less energy. For this reason, hardware specialization is gaining attraction in emerging computer architectures, where hardware accelerators customized in certain functionality are extensively used to deliver orders-of-magnitude increase in performance and energy efficiency for important applications.
Zhang envisions that future computers will continue to incorporate a wide range of hardware accelerators for a variety of application domains. He hopes to develop an integrated design automation framework based on high-level languages to allow domain experts to quickly design higher-quality accelerators without going through the laborious, manual, and error-prone hardware design process.
The proposed design automation framework anchors on the fundamental challenges raised by irregular programs, commonplace in emerging application domains such as computer vision, data mining, machine learning, physical simulation, and social network analytics. While gaining prominence, irregular programs are organized around less-regular data structures and are especially difficult to parallelize with conventional architectures.
Zhang proposes a synergistic hardware/software co-design approach to overcome the many challenges raised by irregular program. More specifically, Zhang plans to devise new algorithms and optimization techniques in a novel architectural synthesis engine that generates softly synthesized accelerators capable of carrying out intelligent run-time optimization without incurring significant hardware overhead.
How can we secure our nation’s electric power infrastructure against malicious cyber attacks? If an attack were to happen, what countermeasures would we have? To develop answers to these questions, Eilyan Bitar was recently awarded an NSF CAREER Award for his proposal, Cyber-Physical Security of Electric Power Systems: Theft and Systemic Failure.
"The physical infrastructure of the U.S. electric grid is aging, over-burdened, and prone to failure," said Bitar. "And the drive to integrate variable renewable energy (such as wind and solar) into the grid, without sacrificing reliability, will require a paradigm shift in how we produce, deliver, and consume energy. At the heart of this transformation is the rapid deployment of the Smart Grid, which integrates new embedded sensing, communication, and computing technologies to improve utilization of existing resources, operational efficiency, and reliability."
However, with the increased reliance of grid operations on complex and actionable data flows, comes the substantial risk of cyber attacks on the corresponding physical and financial systems. By coordinating the manipulation of data transfers from only a small number of remote sensing units, a malicious adversary can mislead the system operator into taking corrective control actions with staggering economic and physical consequences. Situations like this could result in manipulation of electricity market prices and financial derivatives, inefficient dispatch of electric power generation, cascading failures in transmission networks, and physical damage to facilities.
"Through this grant, we'll explore the fundamental challenges associated with securing the electric power infrastructure and electricity markets against cyber attacks," said Bitar. "The various mechanisms through which cyber attacks can manipulate the behavior of the power grid and other cyber-physical systems are not yet well understood. And effective countermeasures are still undeveloped."
By combining expertise at the intersection of power systems, optimization, and stochastic control theory, Bitar and his team intend to develop a mathematical framework and a set of algorithmic tools to serve as the foundation for a new information technology. They expect that this technology will be able to assess the vulnerability of existing power grids, determine the consequence of successful attacks, and develop effective countermeasures to thwart those attacks, innovations that will serve to substantially enhance the security of the United States' critical energy infrastructure and markets.
The intellectual merit of this research is in understanding the capabilities and limitations of imaging systems using diffractive angle-sensitive pixels to analyze the light field. This includes:
- Developing models of how scene statistics are reflected in the output statistics of angle sensitive pixel arrays, and so developing algorithms to extract useful information about the scene, such as depth, 3-D directional motion, and object recognition.
- Understanding how to optimize arrays of angle sensitive pixels to encode scenes at various focal depths, as well as how to best deploy signal selection, conditioning and processing circuits to take advantage of these arrays? Signal properties when encoding real scenes.
- Investigating new integrated diffractive structures that enhance ASP quantum efficiency and spatial resolution, and that filter the light field in new ways.
The broader impacts of this research will include enhanced imaging systems with applications in security, automation, health care, and scientific research, from wildlife tracking to microscopy. This work will also impact the commercial sphere by providing new capabilities in consumer electronics, helping to boost economic growth. These impacts are increased because these systems use standard CMOS manufacturing, and so can be mass-produced at very low size and cost. This research provides an easily understood example of low-level physics driving useful high-level function, providing compelling examples for recruiting and inspiring future engineers.
Alyosha Molnar received his BS from Swarthmore College in 1997, and after spending a season as a deck-hand on a commercial Tuna fishing boat, worked for Conexant Systems for 3 years as an RFIC design engineer. He was co-responsible engineer developing their first-generation direct-conversion receiver for the GSM cellular standard. That chip, and subsequent variants, have sold in excess of 100 million parts. When he entered graduate school at U.C. Berkeley in 2001, Molnar worked on an early, ultra-low-power radio transceiver for wireless sensor networks (receiving his master's degree), and then joined a retinal neurophysiology group where he worked on dissecting the structure and function of neural circuits in the mammalian retina. After receiving his PhD from Berkeley in 2007 he joined the faculty at Cornell University the same year, and presently works on low-power software-defined radios, neural interface circuits, and new integrated imaging techniques.
Systems across the computing spectrum, from cell phones to supercomputers, are increasingly using a heterogeneous mix of general-purpose multicores augmented with programmable graphics processing units (GPUs). Heterogeneity offers a balance between programmability and efficiency, but can also significantly increase complexity at all levels of the computing stack. This project is exploring a new approach based on explicitly encoding and executing a loop iteration space with the goal of elegantly unifying these two types of processors into a single homogeneous computational substrate.
Professor Christopher Batten has been an assistant professor in the School of Electrical and Computer Engineering at Cornell University since January 2010. His research focuses on energy-efficient parallel computer architecture for both high-performance and embedded applications. Christopher received his Ph.D. in electrical engineering and computer science from the Massachusetts Institute of Technology in 2010. From 2007 to 2009, he was a visiting scholar in the new Parallel Computing Laboratory at the University of California at Berkeley. Professor Batten received his M.Phil. in engineering as a Churchill Scholar at the University of Cambridge in 2000, and received his B.S. in electrical engineering as a Jefferson Scholar at the University of Virginia in 1999.
Professors Rajit Manohar, David Albonesi, and Francois Guimbretiere (CS) receive a $700k award from the National Science Foundation for their project entitled "Hardware and Software Architectures for Next-Generation Mobile Platforms." This program will develop a low power platform suitable for systems like e-book readers and smart phones.
The continuous development of high performance integrated circuits has led to an explosion in the communication and computation systems. However the main challenge is that the limited transistor cut-off frequency, maximum power efficiency, and breakdown voltage pose serious constraints on the use of conventional circuit techniques.
The objective of Prof. Ehsan Afshari's research is to design and demonstrate integrated circuits that can generate signals at terahertz frequencies and process information at tens of giga-samples per second with low power consumption in standard silicon processes. The approach is based on intriguing wave propagation phenomena and applying them to nonlinear or inhomogeneous electrical media.
The research is focused on developing a new method of circuit design when the devices operate close to or even beyond their maximum unity power gain frequency. The main contribution is to demonstrate fundamentally novel high frequency signal generation and processing systems with orders of magnitude better performance in terms of maximum output power, operating frequency, power efficiency, and bandwidth compared to the existing methods.
Prof. Afshari was born in Tehran, Iran in 1979. He received the B.S. degree in Electronics Engineering from the Sharif University of Technology, Tehran, Iran and the M.S. and Ph.D. degree in electrical engineering from the California Institute of Technology, Pasadena, in 2003, and 2006, respectively. In August 2006, he joined the faculty in Electrical and Computer Engineering at Cornell University.
Salman Avestimehr, assistant professor in Electrical and Computer Engineering, has received a National Science Foundation Early Career Award for his project "Breaking the Barriers in Wireless Network Information Theory: A Deterministic Approach". The Faculty Early Career Development Program is NSF's most prestigious award in support of the early career-development activities of teacher-scholars.
Information theory is well poised to tremendously impact the design of distributed wireless networks of the future, such as ad-hoc networks. However, the challenge is that most network information theory problems are notoriously difficult and the mathematical barriers that must be overcome are quite high. In this project, prof. Avestimehr aims to overcome this challenge by proposing a new approach, which is based on changing the focus to seek approximate solutions accompanied by guarantees on the gap to optimality. At the heart of this approach is his development of simple, deterministic channel models that capture the main features of the wireless medium, and are utilized to approximate more complex models.
Salman has received a number of awards including the David J. Sakrison Memorial Prize for the most outstanding doctoral research in the EECS department of UC Berkeley in 2008. He also received the Vodafone U.S. Foundation Fellows Initiative Research Merit Award in 2005. Salman joined the School of Electrical and Computer Engineering at Cornell University in 2009.
G. Edward Suh, assistant professor in Electrical and Computer Engineering, recently received a five-year National Science Foundation Faculty Early CAREER Award for his project, "Flexible Multi-Core Substrate for Trustworthy Computing Systems". Multi-core architecture with 4 to 8 cores on a die is a reality today and future generations of processors are expected to contain even more processing cores per chip. The project aims to realize the full potential of large-scale multi-core processors as a secure and trustworthy computing substrate by investigating strong isolation techniques and building a flexible framework for dynamic inspection of various correctness properties. The research will deliver the benefits of hardware support in security and verification without requiring dedicated resources for a single fixed mechanism.
Sunil Bhave, assistant professor in Electrical and Computer Engineering, recently areceived a five-year National Science Foundation Faculty Early CAREER award under the Integrative, Hybrid, and Complex Systems. Prof. Bhave proposes a comprehensive study and design of dielectrically transduced MEMS resonators for communication and computation. The CAREER project focuses on the key challenges for solid- and liquid-dielectrically transduced, high-quality factor RF resonators, including tuning methods, electrode optimization, substrate isolation, and large array synchronization behavior.
Assistant Professor Aaron Wagner has received a National Science Foundation Early Career Award for his proposal "A New Look at the Fundamental Limits of Lossy Network Compression." The Faculty Early Career Development (CAREER) Program is NSF's most prestigious award in support of the early career-development activities of teacher-scholars.
Lossy compression plays a key role in our information economy. By far, most of the information that we generate as a society represents pictures, sounds, and videos, and for this kind of data, lossy compression yields a tremendous reduction in transmission and storage requirements. The aim of Prof. Wagner's project is to understand the fundamental limits of lossy compression, especially in the context of networks, which dominate today's communication infrastructure.
TITLE: Designing with Light: Comparative Analysis and Design of Optical Interconnects for Chip-to-Chip Communication
Abstract: CMOS electronics have become ubiquitous in modern society, continuing to create both technological and economic opportunities in such areas as portable computing and handheld devices. In the past, the capabilities of CMOS processors have been limited internally by transistor density, power consumption, and speed. All of these characteristics have improved consistently with transistor scaling, governed empirically by Moore's Law. However, as CMOS feature sizes decrease into the sub-micron regime, electrical signaling and interconnect problems promise to become the ultimate limit of high performance systems at both the board and chip levels. Integration of optical interconnects into high-performance computing offers a promising and necessary approach to solving the inter-chip communication bottleneck.
Assistant Professor José Martínez has received a National Science Foundation Early Career Award for his proposal "Power-Performance Considerations of Thread-level Parallelism in On-chip Multicore Architectures." The Faculty Early Career Development (CAREER) Program is NSF's "most prestigious award in support of the early career-development activities of those teacher-scholars who most effectively integrate research and education within the context of the mission of their organization."
As the microprocessor industry moves toward multicore solutions (several processor cores on a single chip), performance growth on these inherently power-constrained platforms will increasingly rely upon their ability to support thread-level parallelism efficiently. Martínez's project seeks to develop the necessary insights for the successful design of mechanisms that can address the unique power-performance opportunities and challenges of running parallel applications on multicore chip architectures.
Farhan Rana has received an award of $400,000 for his proposal, "Semiconductor Lasers for Generating High Energy Ultrashort (sub-50 fs) Optical Pulses: From Nanotechnology to Ultrafast Optics." The NSF program is intended to support the early development of academic careers dedicated to stimulating discovery process, in which the excitement of research is enhanced by inspired teaching and enthusiastic learning.